8#include <botan/internal/ghash.h>
10#include <botan/internal/simd_32.h>
12#if defined(BOTAN_SIMD_USE_SSE2)
13 #include <immintrin.h>
14 #include <wmmintrin.h>
22#if defined(BOTAN_SIMD_USE_SSE2)
23 const __m128i BSWAP_MASK = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
24 return SIMD_4x32(_mm_shuffle_epi8(in.raw(), BSWAP_MASK));
25#elif defined(BOTAN_SIMD_USE_NEON)
26 const uint8_t maskb[16] = {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0};
27 const uint8x16_t mask = vld1q_u8(maskb);
28 return SIMD_4x32(vreinterpretq_u32_u8(vqtbl1q_u8(vreinterpretq_u8_u32(in.raw()), mask)));
29#elif defined(BOTAN_SIMD_USE_ALTIVEC)
30 const __vector
unsigned char mask = {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0};
31 return SIMD_4x32(vec_perm(in.raw(), in.raw(), mask));
37 static_assert(M == 0x00 || M == 0x01 || M == 0x10 || M == 0x11,
"Valid clmul mode");
39#if defined(BOTAN_SIMD_USE_SSE2)
40 return SIMD_4x32(_mm_clmulepi64_si128(x.raw(), H.raw(), M));
41#elif defined(BOTAN_SIMD_USE_NEON)
42 const uint64_t a = vgetq_lane_u64(vreinterpretq_u64_u32(x.raw()), M & 0x01);
43 const uint64_t
b = vgetq_lane_u64(vreinterpretq_u64_u32(H.raw()), (M & 0x10) >> 4);
45 #if defined(BOTAN_BUILD_COMPILER_IS_MSVC)
46 __n64 a1 = {a}, b1 = {
b};
49 return SIMD_4x32(
reinterpret_cast<uint32x4_t
>(vmull_p64(a,
b)));
52#elif defined(BOTAN_SIMD_USE_ALTIVEC)
61 }
else if(M == 0x10) {
62 i1 = i1.shift_elems_left<2>();
63 }
else if(M == 0x01) {
64 i2 = i2.shift_elems_left<2>();
65 }
else if(M == 0x00) {
66 i1 = mask_lo.andc(i1);
67 i2 = mask_lo.andc(i2);
70 auto i1v =
reinterpret_cast<__vector
unsigned long long>(i1.raw());
71 auto i2v =
reinterpret_cast<__vector
unsigned long long>(i2.raw());
73 #if BOTAN_COMPILER_HAS_BUILTIN(__builtin_crypto_vpmsumd)
74 auto rv = __builtin_crypto_vpmsumd(i1v, i2v);
76 auto rv = __builtin_altivec_crypto_vpmsumd(i1v, i2v);
79 return SIMD_4x32(
reinterpret_cast<__vector
unsigned int>(rv));
93 X0 = X1.
shl<31>() ^ X1.
shl<30>() ^ X1.
shl<25>();
98 X0 ^= X1.
shr<7>() ^ X1.
shr<2>() ^ X1.
shr<1>();
109 T0 ^= T1.shift_elems_right<2>();
110 T3 ^= T1.shift_elems_left<2>();
112 return gcm_reduce(T0, T3);
128 const SIMD_4x32 lo = (clmul<0x00>(H1, X1) ^ clmul<0x00>(H2, X2)) ^ (clmul<0x00>(H3, X3) ^ clmul<0x00>(H4, X4));
130 const SIMD_4x32 hi = (clmul<0x11>(H1, X1) ^ clmul<0x11>(H2, X2)) ^ (clmul<0x11>(H3, X3) ^ clmul<0x11>(H4, X4));
134 T ^= clmul<0x00>(H1 ^ H1.shift_elems_right<2>(), X1 ^ X1.shift_elems_right<2>());
135 T ^= clmul<0x00>(H2 ^ H2.shift_elems_right<2>(), X2 ^ X2.shift_elems_right<2>());
136 T ^= clmul<0x00>(H3 ^ H3.shift_elems_right<2>(), X3 ^ X3.shift_elems_right<2>());
137 T ^= clmul<0x00>(H4 ^ H4.shift_elems_right<2>(), X4 ^ X4.shift_elems_right<2>());
141 return gcm_reduce(hi ^ T.shift_elems_right<2>(), lo ^ T.shift_elems_left<2>());
146BOTAN_FUNC_ISA(BOTAN_VPERM_ISA)
void GHASH::ghash_precompute_cpu(
const uint8_t H_bytes[16], uint64_t H_pow[4 * 2]) {
148 const SIMD_4x32 H2 = gcm_multiply(H1, H1);
149 const SIMD_4x32 H3 = gcm_multiply(H1, H2);
150 const SIMD_4x32 H4 = gcm_multiply(H2, H2);
153 H2.store_le(H_pow + 2);
154 H3.store_le(H_pow + 4);
155 H4.store_le(H_pow + 6);
159void GHASH::ghash_multiply_cpu(uint8_t x[16],
const uint64_t H_pow[8],
const uint8_t input[],
size_t blocks) {
179 a = gcm_multiply_x4(H1, H2, H3, H4, m3, m2, m1, a);
186 for(
size_t i = 0; i != blocks; ++i) {
190 a = gcm_multiply(H1, a);
193 a = reverse_vector(a);
static SIMD_4x32 load_le(const void *in) noexcept
SIMD_4x32 shift_elems_left() const noexcept
SIMD_4x32 shr() const noexcept
SIMD_4x32 shl() const noexcept
SIMD_4x32 shift_elems_right() const noexcept
#define BOTAN_FUNC_ISA(isa)
#define BOTAN_FORCE_INLINE
#define BOTAN_FUNC_ISA_INLINE(isa)